ASIC Layout Designer

JOB REQUIREMENTS

• Bachelor/master’s degree majored in microelectronics or relevant electrical engineering field (main course: analog circuits, digital circuits, semiconductor device and physics, semiconductor manufacturing);
• Experience in analog/mix-signal integrated circuit layout for ADCs, DACs, PLLs, LDOs, Charge pump, bandgap design;
• In-depth knowledge of TSMC28nm ~ 152nm, SMIC110nm, TZ 180nm BCD SOI technologies and design rules;
• Solid knowledge of industry standard IC layout conventions and rules for reducing layout risk
  Proficiency with Cadence Virtuoso platform as well as Cadence and Mentor Graphics verification and extraction tools Calibre, PVS, Assura, etc;
• Understanding of CMOS process side effect and known how to minimize the risk in layout (e.g.lithographic mismatch, LOD effect, WPE effect, latch-up, ESD, antenna, density stress, etc…);
• Be able to analysis EM and IR drop;
• Skilled in Linux operating system;
• Strong problem-solving skills;
• Fluent English in writing and speaking.

Preferred Skills and Experience

• Work experience in an international company or abroad;
• Programming: shell, skill, python, tcl;
• Experience in leading a full chip layout from floorplan to tape-out;
• Auto place and route experience for non-timing critical design is a plus.